The present application relates generally to semiconductor devices, and more specifically to methods for manufacturing fin field effect transistors.
Fully-depleted devices such as fin field effect transistors (FinFETs) are candidates to enable scaling of next generation gate lengths to 14 nm and below. Fin field effect transistors (FinFETs) present a three-dimensional architecture where the transistor channel is raised above the surface of a semiconductor substrate, rather than locating the channel at or just below the surface. With a raised channel, the gate can be wrapped around the sides of the channel, which provides improved electrostatic control of the device.
The manufacture of FinFETs typically leverages a self-aligned process to produce extremely thin fins, e.g., 20 nm wide or less, on the surface of a substrate using selective-etching techniques. A gate structure is then deposited to contact multiple surfaces of each fin to form a multi-gate architecture.
The gate structure may be formed using a gate-first or a gate-last fabrication process. A gate-last process, such as a replacement metal gate (RMG) process, utilizes a sacrificial or dummy gate, which is typically replaced by a functional gate after device activation, i.e., after dopant implantation into source/drain regions of the fins and an associated drive-in anneal, in order to avoid exposing the functional gate materials to the thermal budget associated with activation.
Prior to removing the sacrificial gate and forming a functional gate, a gate cut module may be used to sever (i.e., segment) the sacrificial gate in order to define and isolate plural adjacent devices. In association with such a process, portions of the sacrificial gate are removed to form openings that are backfilled with an etch selective dielectric material, i.e., isolation layer, that provides a barrier between adjacent functional gates following removal and replacement of the remaining sacrificial gate material. At advanced nodes, however, notwithstanding recent developments, it remains a challenge to define a gate cut opening with both the desired critical dimension(s) and alignment precision amidst a plurality of densely-arrayed fins.
In comparative structures, misalignment of the gate cut can present a challenging geometry for the conformal deposition of various layers between a fin and the isolation layer filling the gate cut opening adjacent to the fin. Following deposition of a high-k (gate dielectric) layer over the fins, for example, a reliability anneal to improve the properties of the high-k material may include, prior to the annealing step, the deposition of a sacrificial stack of layers, including a conformal layer of titanium nitride over the high-k layer, and the deposition of a layer of amorphous silicon over the layer of titanium nitride.
In misaligned structures where the fin-to-isolation layer distance is less than the design intent, the layer of amorphous silicon may pinch off and incompletely fill the space between the fin and the isolation layer, thus forming a void. The void may trap oxygen that, during the high temperature (e.g., 1000° C.) anneal, causes oxidation of the amorphous silicon and the formation of a layer of silicon dioxide within the void.
Following the anneal, removal of the sacrificial layer of amorphous silicon and the sacrificial layer of titanium nitride may proceed with an initial etching step to strip the native oxide (silicon dioxide) from the surface of the amorphous silicon layer using, for example, a wet etch chemistry including HF, followed by a further etching step to remove the amorphous silicon and the titanium nitride. Hot ammonia, for example, may be used to etch amorphous silicon.
In conjunction with the foregoing process, following removal of the amorphous silicon and the layer of titanium nitride, a residual layer of silicon dioxide formed within one or more voids may remain within the space between the fin and the adjacent isolation layer and interfere with the deposition of layers within that space during subsequent processing. At this stage of processing, an oxide etch suitable to remove the silicon dioxide residue would damage the exposed high-k layer. As such, complete removal of the silicon dioxide layer poses a challenge.
In addition to, or in lieu of the foregoing, misalignment of the gate cut may result in the undesired pinch off of other later-formed layers within the gap between the fin and the isolation layer, such as a work function metal (WFM) layer formed over the fins as part of a functional gate stack.